1. Field of the Invention
The present invention generally relates to computer systems, and more specifically to a method of configuring a computer system having peripheral devices, particularly adapter devices (such as graphics adapters or network adapters) which require configuration after a system reset, and which are interconnected to the system's processor using a peripheral (local) bus.
2. Description of Related Art
A typical structure for a conventional computer system includes one or more processing units connected to a system memory device (random access memory or RAM) and to various peripheral, or input/output (I/O), devices such as a display monitor, a keyboard, a graphical pointer (mouse), and a permanent storage device (hard disk). The system memory device is used by a processing unit in carrying out program instructions, and stores those instructions as well as data values that are fed to or generated by the programs. A processing unit communicates with the other components by various means, including one or more interconnects (buses), or direct memory-access channels. A computer system may have many additional components, such as serial and parallel ports for connection to, e.g., printers, and network adapters. Other components might further be used in conjunction with the foregoing; for example, a display adapter might be used to control a video display monitor, a memory controller can be used to access the system memory, etc.
Several different bus designs have been developed for interconnecting the various computer components. The original personal computer (PCs) introduced by International Business Machines Corp. (IBM--assignee of the present invention) used an "expansion" bus referred to as the XT bus, which allowed a user to add various optional devices, such as additional memory (RAM), sound cards, telephone modems, etc. This early design was improved upon by adding more data and address lines, new interrupt lines, and direct memory-access (DMA) control lines, to create the well-known AT bus, which is also referred to as the Industry Standard Architecture (ISA) bus. The AT design allowed the microprocessor to run at a faster speed than the expansion bus. A 32-bit extension to this bus was later created, which is referred to as the Extended Industry Standard Architecture (EISA). Another 32-bit expansion bus developed by IBM is the Microchannel Architecture (MCA) bus.
In addition to the foregoing designs, several other bus designs have been developed allowing the use of a system bus which interconnects the processor and the system memory device(s), along with a separate, local bus which interconnects the peripheral devices to the system bus (using a bus bridge). Two well-known standards are the Video Electronics Standards Association (VL) bus, and the Peripheral Component Interconnect (PCI) bus.
The PCI specification allows up to four PCI-compliant expansion cards to be installed in "slots" constructed along the PCI bus (up to 10 loads can be placed on the bus, but each device requires two loads as a connector for a slot constitutes a load, so four devices can be added at most (8 loads), since the bridge also counts as a load). A PCI local bus system uses a PCI controller, which must be installed in one of the PCI-compliant slots. An expansion bus controller for a system's ISA, EISA, or MCA slots can optionally be installed as well, providing increased synchronization for all of the system's bus-installed resources. A PCI controller exchanges data with the microprocessor either 32 bits or 64 bits at a time, depending on the implementation, and allows certain "intelligent" PCI-compliant adapters to perform tasks concurrently with the microprocessor, using a technique called bus mastering. The PCI specification also allows for multiplexing, a technique that permits more than one electrical signal to be present on the bus at one time.
A typical PCI system 10 is illustrated in FIG. 1. System 10 includes a central processing unit (CPU) 12, firmware or read-only memory (ROM) 14, and a dynamic random access memory (DRAM) 16 which are all connected to a system bus 18. CPU 12, ROM 14 and DRAM 16 are also coupled to a PCI local bus 20 using a PCI host bridge 22. PCI host bridge 22 provides a low latency path through which processor 12 may access PCI devices mapped anywhere within bus memory or I/O address spaces. PCI host bridge 22 also provides a high bandwidth path to allow the PCI devices to access DRAM 16.
Attached to PCI local bus 20 are a local area network (LAN) adapter 24, a small computer system interface (SCSI) adapter 26, an expansion bus bridge 28, an audio adapter 30, and a graphics adapter 32. Lan adapter 24 is used to connect computer system 10 to an external computer network 34. SCSI adapter 26 is used to control high-speed SCSI disk drive 36. Expansion bus bridge 28 is used to couple an ISA expansion bus 38 to PCI local bus 20. As shown, several user input devices are connected to ISA bus 38, including a keyboard 40, a microphone 42, and a graphical pointing device (mouse) 44. Other devices may also be attached to ISA bus 38, such as a CD-ROM drive 46. Audio adapter 30 controls audio output to a speaker 48, and graphics adapter 32 controls visual output to a display monitor 50.
In earlier computer systems, all of the peripheral components had to be connected (inserted in the PCI or ISA slots) at the time that the computer was first turned on, in order to properly register (initialize) the devices with the computer's operating system. These devices are checked during the system's power-on self test (POST), which includes a set of routines stored in ROM 14 (also referred to as read-only storage, or ROS) that test the peripherals to see if they are properly connected and operating. If problems with any of the devices are detected, these routines alert the user by sounding a series of beeps or displaying a message, often accompanied by a diagnostic numeric value, to the standard output device or standard error device (usually the display screen).
In the earlier systems, if a device were simply not present during the POST, then it would not be recognized when it was later inserted in a slot (while the computer was still running). Instead, those systems were required to be "rebooted" in order to be able to communicate with and utilize the later-added devices. "Rebooting" refers to the restarting of a computer system by reloading its most basic program instructions, viz., the operating system. A system can be rebooted using the software itself (a warm boot) or by actuating the system's hardware, i.e., the reset or power buttons (a cold boot). After rebooting, the new device can be identified using various techniques. See, e.g., U.S. Pat. No. 5,594,873.
More recent computer systems have the ability to recognize devices which are added to a bus while the computer is operating, that is, without having to reboot the system. One example is the "plug and play" specification, which allows a PC to configure itself automatically to work with peripherals. A user can "plug" in a peripheral and "play" it without manually configuring the system. Plug and play operation requires both ROM that supports the specification, and a special expansion card. While this approach allows the system to recognize a newly added device, it is still often necessary to reset the system in order to properly initialize the device with the operating system. A further improvement in this area is the "hot-plug" specification, wherein separate reset lines are provided for each peripheral device, such that a device can be initialized with the operating system without requiring the entire system to be rebooted (this ability of the device/system is referred to as "hot-pluggable").
One problem that persists in the initialization of peripheral devices is that, following a deactivation of the reset signal (RST#), there may be a long time before an adapter is prepared to respond to configuration cycles with even a RETRY response (which is used to indicate that the adapter is functioning, but it is currently too busy to respond to the initialization). As a result, following deactivation of RST#, a system may consider an adapter as not present or defective if it does not respond. If the device responds to configuration or regular (non-configuration) cycles with RETRY, the PCI bus and/or the system processor can stall, resulting in the requirement to reboot the system.
Previously, this problem has not been significant, but now there are a number of situations that may result in an adapter card and/or a group of adapters being reset while the processor and the rest of the I/O subsystem remains operational. One factor that contributes to this problem is the increased complexity of adapters, such as an adapter that must initialize a programmable logic array (PLA) following RST# deactivation before it can handle a configuration cycle or even respond with RETRY, or an adapter with an on-board processor that must load registers and complete other initialization steps before it can handle a configuration cycle or even respond with RETRY. Another factor is the provision of separate reset lines to the adapters, such as is provided in the hot-plug specification and similar PCI power management specifications, or in diagnostic analysis of an individual card while the rest of the system and PCI I/O subsystem remains operational.
In light of the foregoing, it would be desirable to devise a method of avoiding rebooting requirements associated with delayed initialization responses from peripheral devices. It would be further advantageous if, following configuration completion, the adapter were prepared to respond to normal (non-configuration) cycles without a RETRY response.